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PRELIMINARY TECHNICAL DATA
a
Low Voltage 1.2 V to 5.5 V, Bidirectional, Logic Level Translators Preliminary Technical Data ADG3304
FEATURES Bidirectional Level Translation Operates from 1.2 V to 5.5 V 12 Bump WLCSP package and 14-lead TSSOP Low Quiescent Current <5A APPLICATIONS SPITM, MicrowireTM and I2CTM Translation Low Voltage ASIC level Translation Smart Card Readers Cell Phones & Cell-Phone Cradles Portable Communication Devices Telecommunicatons Equipment Network Switches and Routers Storage Systems (SAN/NAS) Computing/Server Applications GPS Portable POS Systems Low Cost Serial Interfaces FUNCTIONAL BLOCK DIAGRAM
VCCA A1 A2 A3 A4 EN GND VCCY Y1 Y2 Y3 Y4
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG3304 is a 4-Channel bidirectional level translator. Its function is to provide level shifting in a multivoltage system. The voltage applied to VCCA sets up the logic levels on the A side of the device, while VCCY sets the levels on the Y side. In this way, signals applied to the VCCA side of the device appear as VCCY compatible logic on the other side of the device and vice versa as the device is designed to handle bidirectional signals. The device is guaranteed for operation over the supply range 1.2 V to 5.5 V. These devices are suited to applications like data transfer between a low voltage DSP/Controller and a higher voltage device. Other applications include high end consumer products where constant changes to the chipset desgins result in multiple supply levels in the application. VCCY operates from +1.65 to 5.5 V while VCCA from +1.2 to VCCY. VCCA must always operate from a supply that is lower than VCCY. When the device Enable pin (EN) is pulled low, the Ax and Yx inputs/outputs are tri-stated. The EN pin is driven high for normal operation. EN pin is referred to VCCA voltage.
1. 2. 3.
Bidirectional Level Translation. The ADG3304 is fully guaranteed from 1.2 V to 5.5 V supply range. 14 lead TSSOP and 12 lead WLCSP package.
REV. PrC Feb 2004
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2004
PRELIMINARY TECHNICAL DATA
ADG3304-SPECIFICATIONS1 specifications T (V = +1.65 to 5.5 V, V = +1.1 to V , GND = 0 V, All
CCY CCA CCY
MIN
to TMAX unless otherwise noted)
Min Typ2 Max Units V V V V V V V V A A pF pF
Parameter LOGIC INPUTS/OUTPUTS Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Input Capacitance3 Output Capacitance3
Symbol VIH VIL VOH VOL II IO CIN CO
Conditions
VCCY -0.4 VCCA -0.4 IOH = 20 A, IOH = 20 A, IOL = 20 A, IOL = 20 A, 0 VIN 3.6 V 0 VIN 3.6 V f = 1 MHz, VA/Y = VCCA/Y or GND f = 1 MHz, VA/Y = VCCY/A or GND 0.4 0.4 VCCY -0.4 VCCA -0.4 0.4 0.4 1 1 5 5
SWITCHING CHARACTERISTICS3 3.3V 0.3V VCCA VCCY 5V 0.5V Propagation Delay, tPD Y-A A-Y Rise Time tR_Y Fall Time tF_Y Rise Time tR_A Fall Time tF_A Maximum Data Rate Channel To Channel Skew tSKEW Part To Part Skew tPPSKEW 1.8V 0.15V VCCA VCCY 3.3V 0.3V Y-A Propagation Delay, tPD A-Y Rise Time tR_Y Fall Time tF_Y Rise Time tR_A Fall Time tF_A Maximum Data Rate Channel To Channel Skew tSKEW 1.2V 0.1 V VCCA VCCY 3.3 0.3 V Propagation Delay, tPD Y-A A-Y Rise Time tR_Y Fall Time tF_Y Rise Time tR_A Fall Time tF_A Maximum Data Rate Channel To Channel Skew tSKEW 2.5V 0.2V VCCA VCCY 3.3V 0.3V Propagation Delay, tPD Y-A A-Y Rise Time tR_Y Fall Time tF_Y Rise Time tR_A Fall Time tF_A Maximum Data Rate Channel To Channel Skew tSKEW POWER REQUIREMENTS Power Supply Voltages Quiescent Power Supply Current VCCY VCCA ICCY ICCA
RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50,
CA = 15 pF CY = 50 pF CY = 50 pF CY = 50 pF CA = 15 pF CA = 15 pF CY = 50 pF, CA = 15 pF CY = 50 pF, CA = 15 pF CY = 50 pF, CA = 15 pF CA = 15 pF CY = 50 pF CY = 50 pF CY = 50 pF CA = 15 pF CA = 15 pF CY = 50 pF, CA = 15 pF CY = 50 pF, CA = 15 pF
5 5 5 5 5 5 40 tbd tbd 10 15 10 10 10 10 35 5 20 20 15 15 15 15 20 5 8.5 8.5 8.5 8.5 8.5 8.5 40 10 1.65 1.1 5.5 5.5 5 5
ns ns ns ns ns ns Mbps ns ns ns ns ns ns ns ns Mbps ns ns ns ns ns ns ns Mbps ns ns ns ns ns ns ns Mbps ns V V A A
RS = 50, CA = 15 pF RS = 50, CY = 50 pF RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, RS = 50, CY = 50 pF CY = 50 pF CA = 15 pF CA = 15 pF CY = 50 pF, CA = 15 pF CY = 50 pF, CA = 15 pF CA = 15 pF CY = 50 pF CY = 50 pF CY = 50 pF CA = 15 pF CA = 15 pF CY = 50 pF, CA = 15 pF CY = 50 pF, CA = 15 pF
Digital Inputs = 0 V or VCCY Digital Inputs = 0 V or VCCA
NOTES 1 Temperature range is as follows: B Version: -40C to +85C. 2 All typical vlaues are at T A = +25C unless otherwise stated. 3 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
-2-
REV. PrC
PRELIMINARY TECHNICAL DATA ADG3304
ABSOLUTE MAXIMUM RATINGS1
(T A = 25C unless otherwise noted)
VCCY to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VCCA to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Digtal Inputs (A) . . . . . . . . . . . . . . -0.3 V to (VCCA +0.3V) Digtal Inputs (Y) . . . . . . . . . . . . . . -0.3 V to (VCCY +0.3V) EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150C 14 Lead TSSOP JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 150C/W Lead Temperature, Soldering (10seconds) . . . . . . . 300C IR Reflow, Peak Temperature (<20 seconds) . . . +235C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specifcation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
Pin Configuration 14 Lead TSSOP (RU-14)
VCCA 1 A1 2 A2 3 A3 4 A4 5 NC 6 GND 7 ADG3304 (Not to Scale) 14 VCCY 13 Y1 12 Y2 11 Y3 10 Y4 9 NC 8 EN
12 Lead WLCSP (CB-12)
a 1 A1 2 A2 3 A3 4 A4
b
c
VCCY Y1 VCCA Y2 EN Y3
GND Y4
ORDERING GUIDE
Model ADG3304BRU ADG3304BCB
Temperature Range -40C to +85C -40C to +85C
Package Description TSSOP WLCSP
Package Option RU-14 CB-12
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG3304 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. PrC
-3-
PRELIMINARY TECHNICAL DATA ADG3304
GENERAL DESCRIPTION
The ADG3304 level translator allows the required level shifting necessary for data transfer in a system where multiple voltages are used. The device requires two supplies, VCCA and VCCY. These supplies set the logic levels on each side of the device. The device translates data present on the VA side of the device to the higher voltage level at the VY side of the device. Similarly, as the device is capable of bidirectional translation, data applied to the VY side will be translated to the voltage referenced to VA.
Level Translator Architecture
The forward channel consists of a string of inverters and a level translator, while the reverse channel consists simply of inverters. A level translator is not required in the reverse path (Y-A) as the supply voltage VCCY must always be greater than or equal to VCCA. A current limiting resistor is used in series with each channel to prevent any contention issues, see figure 1.
As the driven side has to drive a load capacitance through this 6k resistance, one shot generators are used to drive large mos devices in the output stage to help speed up the rate of switching. The output stage is inactive and three state except when transistions are present on either side of the translator. When this happens the one shot fires turning on the output stage and driving the load capacitance faster than if it were driven through the resistor. As the device is bi-directional, both input stages will be active during this period. While this design gives maximum speed from the device, it can result in some current driving back into the source driving the input of the translator. To ensure correct operation, the input driver should meet the following requirements - 50 maximum output impedance with minimum of 20mA output current when driving 20Mbps.
Enable Operation
When pulled low, the EN input allows the user to tri-state both sides (A and Y) of the level translator. EN pin is referred to VCCA voltage.
VCCA One Shot Generator
VCCY
6k A Y
One Shot Generator
6k
Figure 1. Simplified Functional Diagram of one channel.
-4-
REV. PrC
PRELIMINARY TECHNICAL DATA ADG3304
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead TSSOP (RU-14)
PR04860-0-4/04(PrC)
0.201 (5.10) 0.193 (4.90)
14 8
0.177 (4.50) 0.169 (4.30)
1
7
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0079 (0.20) 0.0035 (0.090)
0.256 (6.50) 0.246 (6.25)
SEATING PLANE
8 0
0.028 (0.70) 0.020 (0.50)
12-Lead WLCSP (CB-12)
0.079 (2.0) Pin 1 Identifier 0.079 (2.0) 0.0035 (0.09)
1 0.059 (1.5) Top View 0.059 (1.5)
0.013 (0.32)
Bottom View
0.0035 (0.09) 0.0086 (0.22) 0.0224 (0.57)
0.0197 (0.5)
0.0138 (0.35) Side View
REV. PrC
-5-

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